You can use the Synopsys Synplify design entry/synthesis tool to create, synthesize, and optimize a project and then generate an Verilog Quartus Mapping File (.vqm) for compilation in the Quartus II software. The following topics describe the typical flow with the Synplify software and the Quartus II software:
You can also run the Synplify software automatically from within the Quartus II software to synthesize a design using the NativeLink feature.
You can use Altera-provided megafunctions in the Synplify software by using the MegaWizard Plug-In Manager to create custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions and Altera megafunctions. Refer to the following topics for information on how to use specific megafunctions:
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Creating and Instantiating a VHDL Function for Use with the Synplify Software
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Creating and Instantiating a Verilog HDL Function for Use with the Synplify Software
You can use the same procedures and principles to use similar megafunctions in other designs.
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More information is available on other EDA design entry/synthesis tools on the Altera website. |

