About Using the Quartus II Software with Other EDA Tools

You can direct the Quartus II software to make use of third-party EDA tools in a number of ways. Some tools, such as simulation and timing analysis tools can be directed to run automatically as part of a compilation from within the Quartus II software. Many tools can be used or configured from the EDA Tool Settings pages of the Settings dialog box

• You can use the Mentor Graphics DK Design Suite, LeonardoSpectrum, and Precision RTL Synthesis, Synopsys Synplify and Synplify Pro software to synthesize a design as part of a normal compilation.

• You can run the Aldec Active-HDL and Riviera-PRO, Cadence Incisive NCSim software for Verilog HDL and VHDL, Mentor Graphics ModelSim-Altera (OEM), ModelSim PE/SE (non-OEM), Synopsys VCS and Synopsys VCS MX simulation tools, and Synopsys PrimeTime timing analysis tool automatically after a normal compilation, or from within the Quartus II software after an initial compilation.

• You can direct the Quartus II software to generate output files for performing physical synthesis with Precision Physical and Synplify Premier software.

• You can generate files for use in formal verification of a design with the Cadence Encounter Conformal or Synopsys Formality software.

• You can generate files for use in several different kinds of board-level verification processes, including Stamp model files for timing verification with the Mentor Graphics TAU software, FPGA Xchange-Format File (.fx for use with Mentor Graphics I/O Designer software, PartMiner edaXML-Format Files (.xml) for symbol generation in the Mentor Graphics DxParts software, and IBIS Output Files (.ibs) and HSPICE Simulation Deck files (.sp) for signal integrity analysis.

You can use the NativeLink feature to run EDA design entry/synthesis tools, simulation, and timing analysis tools automatically from within the Quartus II software as described in the following flow:

In the EDA Tool Settings pages of the Settings dialog box, you can specify options for the EDA tools you want to use. You can direct the Quartus II software to run a design entry or synthesis tool to synthesize the design as part of a normal compilation. You can also direct the Quartus II software to run a simulation or timing analysis tool automatically after compilation. You can specify additional options for input and output files in the following pages that are under the EDA Tool Settings page:

• In the Design Entry and Synthesis page, you can specify an EDA design entry or synthesis tool and specify EDA tool input settings, including specifying a Library Mapping File (.lmf) for processing EDIF Input Files, VHDL Design Files, Verilog Design Files, Verilog Quartus Mapping Files, and AHDL Text Design Files that were generated by other design entry or synthesis tools.

• In the Simulation page and Timing Analysis page, you can specify EDA tools for simulation and timing analysis and specify HDL output settings for generating Verilog VHD and VHDL Output Files and SDF Output Files for use with other simulation or timing analysis tools. You can also specify settings for running the Mentor Graphics ModelSim, ModelSim-Altera, NCSim (NC-VHDL or NC-Verilog), VCS, or VCS MX simulation software with a test bench.

• In the More Timing Analysis Settings dialog box, you can specify options for running the PrimeTime software in shell mode or GUI mode on a Linux workstation.

• In the Board-Level page, you can specify various board-level tools.

• In the Formal Verification page, you can specify an EDA formal verification tool.

• In the Physical Synthesis page, you can specify an EDA physical synthesis tool and specify settings for performing physical synthesis with other EDA tools.

The Quartus II software can generate files for use with most industry-standard EDA simulation and timing analysis tools, including Aldec Active-HDL; Cadence Incisive NCSim (NC-Verilog and NC-VHDL); Mentor Graphics Tau software; Mentor Graphics ModelSim and ModelSim-Altera software; and Synopsys VCS, VCS MX, and PrimeTime software.

In addition to Verilog Output Files, VHDL Output Files, and SDF Output Files, you can generate the following types of files after compilation of the design with the Start EDA Netlist Writer command:

• Stamp model files

• PartMiner edaXML-Format Files (.xml)

• FPGA Xchange-format files (.fx) for symbol generation in board-level verification tools

• IBIS Output Files (.ibs)

• HSPICE Simulation Deck files (.sp)

• Script files to generate Value Change Dump File (.vcd) in EDA simulation tools

• Boundary-Scan Description Language Files (.bsd)

The Quartus II software can read EDIF Input File (.edf), Verilog Quartus Mapping File (.vqm), VHDL Design File (.vhd), and Verilog Design File (.v) created by most popular design entry/synthesis tools, including Synopsys Design Compiler, Mentor Graphics LeonardoSpectrum and Precision RTL Synthesis, Synopsys Synplify and Synplify Pro, and ViewDraw software.

Processing Menu Commands

You can use the Start Test Bench Template Writer command to generate Verilog Test Bench Files (.vt) and VHDL Test Bench Files (.vht) for simulation with other EDA simulation tools.

You can also use the Start EDA Synthesis command to run an EDA design entry/synthesis tool from within the Quartus II software.

You can use theStart EDA Physical Synthesiscommand to run an EDA  physical synthesis tool from within the Quartus II software.

You can use the Start EDA Netlist Writer to generate VHDL Output File (.vho),Verilog Output Files (.vo), and Standard Delay Format Output Files (.sdo) for a design. You can compile a design and then specify different EDA tool settings and regenerate the netlist files without recompiling the design.

Tools Menu Commands

The EDA RTL Simulation Tool and EDA Gate-Level Simulation Tool commands allow you to run simulation tools automatically from within the Quartus II software after an initial compilation.

The Run EDA Timing Analysis Tool command allows you to run timing analysis tools automatically from within the Quartus II software after an initial compilation.