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Please contact your local Altera sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
The Altera® Crest Factor Reduction reference design is a high-performance, highly parameterizable crest factor reduction processor, designed and delivered using Altera® DSP Builder Advanced Blockset tool. It is based on the peak cancellation algorithm.
The design methodology allows you to go from system definition and simulation, using the industry-standard MathWorks® Simulink® tools, to system implementation in a matter of minutes. System definition in both fixed and floating point number representations is supported. DSP Builder Advanced Blockset uses a high-level synthesis technology that optimizes the untimed netlist into low-level, pipelined hardware targeted to your chosen FPGA device and chosen clock rate. It provides a constraint-driven design methodology through system-level parameters. You specify the desired fmax; the tool then inserts sufficient pipelining, balances delays and maintains the data path algorithm accuracy. The result is that DSP Builder Advanced Blockset produces an implementation which is optimized to the same level as hand-coded HDL, so the designer does not have to make a design productivity verses efficient implementation compromise.
For system engineers, the Advanced Blockset introduces them to FPGA design without having to immediately comprehend all of the tradeoffs associated with other hardware design flows. For hardware engineers, it allows designs to be completed in an abstract format, eliminating the need for timing closure through auto-pipelining and generation of any control logic. To further optimize the design flow, DSP Builder Advanced Blockset allows a common development environment and test bench to be used in developing complex algorithms. This facilitates rapid implementation of changes at the system level, and eliminates barriers between system algorithm and FPGA hardware engineering efforts.
For the Altera® Crest Factor Reduction reference design, the DSP Builder Advanced Blockset offers a high-level design entry point that lets designers explore the design space and easily customize their design parameters. It also provides a path to easy integration into Qsys, Altera's system integration tool.
For further information, contact your local Altera representative.
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These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
