Verilog

The following examples provide instructions for implementing functions using Verilog HDL. For more information on Verilog support, refer to Quartus® II Help.

For more examples of Verilog designs for Altera^® devices, refer to the Recommended HDL Coding Styles (PDF) chapter of the Quartus II Handbook. You can also access Verilog HDL examples from the language templates in Quartus II software. For additional hand-crafted techniques you can use to optimize design blocks for the adaptive logic modules (ALMs) in many Altera devices, refer to the Advanced Synthesis Cookbook: A Design Guide for Stratix^® II, Stratix III, and Stratix IV Devices (PDF).

Verilog Embedded Processor Functions

• Fast Nios^® II Hardware Design Example

Verilog Communications Functions

• POS-PHY LEVEL4 (SPI4.2) Loopback Design on Stratix III/Stratix IV Development Board

Verilog Arithmetic Functions

• Adder/Subtractor
• Binary Adder Tree
• Ternary Adder Tree
• Parameterized Counter
• Behavioral Counter
• Gray Counter

Verilog External Memory Interfaces Functions

• Four DDR3 ALTMEMPHY-Based Controllers for Stratix IV FPGAs
• Interfacing with a 64-bit DDR3 SDRAM UDIMM Interface at 400 MHz in a Stratix IV FPGA
• 8-Bit Wide DDR2 ALTMEMPHY-Based SOPC Builder Integrated in Cyclone III FPGAs
• 8-Bit Wide DDR3 UniPHY-Based Qsys Integrated in Stratix IV FPGAs
• Interfacing 400-MHz RLDRAM II in a Stratix IV FPGA
• Interfacing 350-MHz QDR II+ SRAM in a Stratix IV FPGA
• Interfacing with a 64-bit DDR3 SDRAM UniPHY Interface at 533 MHz in a Stratix IV FPGA
• Interfacing with a 72-bit DDR2 SDRAM UniPHY Interface at 400 MHz in a Stratix III FPGA
• Implementing Multiple Memory Interface Using UniPHY in a Stratix IV FPGA

Verilog Memory Functions

• Dual Clock Synchronous RAM
• Single Clock Synchronous RAM
• Parameterized RAM with Separate Input and Output Ports
• True Dual-Port RAM with a Single Clock
• Single-Port RAM

Verilog Bus and I/O Functions

• High-Speed Differential I/O Capability
• Tri-State Instantiation
• Bidirectional Pin

Verilog Logic Functions

• 1x64 Shift Register
• 8x64 Shift Register with Taps
• Counter with Asynchronous Reset
• Instantiating a DFFE
• Synchronous State Machine
• Verilog HDL Templates for State Machines

Verilog Digital Signal Processing (DSP) Functions

• Verilog HDL Template for Inferring DSP Blocks in Stratix III and IV FPGAs
• Achieving Unity Gain in Block Floating-Point IFFT+FFT Pair
• Coefficient Reload for FIR Compiler
• FFT with 32K-Point Transform Length
• Signed Multiplier with Registered I/O
• Signed Multiplier-Adder
• Unsigned Multiplier
• Unsigned Multipier-Accumulator

Other Verilog Functions

• Creating a Hierarchical Design
• Instantiating MAX+PLUS^® II Primitives

How to Use Verilog HDL Examples

Altera provides Verilog HDL design examples as downloadable executable files or displayed as text in your web browser. Select the executable file link to download the file to your hard disk. To use Verilog HDL examples displayed as text in your Quartus II software (or legacy MAX+PLUS II software), copy and paste the text from your web browser into the Text Editor. Make sure that the file name of the Verilog HDL design file (.v) corresponds to the entity name in the example. For example, if the entity name is myram, save the file as myram.v.

Design Examples Disclaimer

These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.