PLL Clock Management Features in Altera FPGAs

Altera^® FPGAs offer feature-rich phase-locked loops (PLLs) that provide robust clock management capabilities and synthesis for device clock management, external system clock management, and high-speed I/O pin interfaces. The PLLs can feed the global clock network or I/O pins. One of our newest FPGA families, Stratix^® V FPGAs, offer fractional PLLs (fPLLs) that deliver increased clocking flexibility and replace external voltage-controlled crystal oscillators (VCXOs).

Table 1 summarizes and compares the PLL features available in our latest FPGAs.

Notes:

1. C counters range from 1 through 32 if the output clock uses a 50 percent duty cycle. For any output clocks using a non-50 percent duty cycle, the post-scale counter ranges from 1 through 16.
2. C counters range from 1 through 512 if the output clock uses a 50 percent duty cycle. For any output clocks using a non-50 percent duty cycle, the post-scale counter ranges from 1 through 256.
3. The PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For high-speed differential I/O pins, the device uses a data channel to generate the transmitter output clock (txclkout).
4. PLL5 and PLL6 do not have dedicated clock outputs. The same PLL clock output drives three single-ended or three differential I/O pairs. This is only supported in PLL_1 and PLL_3 of the EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
5. This is not applicable for MPLL5 and MPLL6.
6. This is not applicable for GPLL3 and GPLL4.
7. This is only applicable when MPLLs are used for transceiver clocking.
8. pllena feature is not supported in Stratix IV, Stratix III, Arria II GX, Cyclone IV, and Cyclone III devices.
9. The global (GCLK) or regional (RCLK) clock input can be driven by an output from another PLL, a clock pin-driven global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal or general purpose I/O pin cannot drive the PLL.

To view the PLL features available in all Altera FPGAs, refer to PLL Features in Altera FPGAs.

Documentation

Detailed information about the PLLs available in the Altera device families can be found in the appropriate device family handbook:

• Clock Networks and PLLs in Stratix IV Devices (PDF)
• Clock Networks and PLLs in Stratix III Devices (PDF)
• PLLs in Stratix II and Stratix II GX Devices (PDF)
• General-Purpose PLLs in Stratix & Stratix GX Devices (PDF)
• Clock Networks and PLLs in Cyclone IV Devices (PDF)
• Clock Networks and PLLs in Cyclone III Devices (PDF)
• PLLs in Cyclone II Devices (PDF)
• Using PLLs in Cyclone Devices (PDF)
• Clock Networks and PLLs in Arria II Devices (PDF)
• PLLs in Arria GX Devices (PDF)

Additional related information is available in the following documents and web page:

• Phase-Locked Loop (ALTPLL) Megafunction User Guide (PDF)
• AN 454: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices (PDF)
• AN 367: Implementing PLL Reconfiguration in Stratix II Devices (PDF)
• AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices (PDF)
• AN 507: Implementing PLL Reconfiguration in Cyclone III Devices (PDF)
• AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices (PDF)
• Possible Causes for PLL Loss of Lock web page